library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity traffic is 
port(CLK :in std_logic;
RSTN : in std_logic;
I1 :in std_logic ;
I2 :in std_logic ;
I3 :in std_logic ;                -- logic values from irs and ldr
I4 :in std_logic ;
LDR :in std_logic ;
--C1 :in std_logic_vector(2 downto 0); -- maximum count , in(0) stores the max counts index
--C2 :in std_logic_vector(2 downto 0) ;
--C3 :in std_logic_vector(2 downto 0);
--C4 :in std_logic_vector(2 downto 0);
--in0: in std_logic_vector(2 downto 0); --stores maximum 
--in1: in std_logic_vector(2 downto 0);
--in2: in std_logic_vector(2 downto 0); -- we get these from the compare block
--in3: in std_logic_vector(2 downto 0);
	T1 : out std_logic_vector(2 downto 0);
	T2 : out std_logic_vector(2 downto 0);
	T3 : out std_logic_vector(2 downto 0);      --3 bit vector outputs to traffic light s
	T4 : out std_logic_vector(2 downto 0);
P1 : out std_logic_vector(1 downto 0);
P2 : out std_logic_vector(1 downto 0);     --2 bit vector outputs to pedestrians
P3 : out std_logic_vector(1 downto 0);
P4 : out std_logic_vector(1 downto 0));  --24 in/out pins
end entity traffic ;
 architecture functionality of traffic is 
 component vehicle_counter is             --counter component
 port(CLK :in std_logic;
RSTN : in std_logic;
I1 :in std_logic ;
	outp : out std_logic_vector(4 downto 0));
end component ;
component compare_block is 
port(CLK :in std_logic;                 --compare component
RSTN : in std_logic;
r1 :in std_logic ;
r2 :in std_logic ;
r3 :in std_logic ;
r4 :in std_logic ;
C1 : out std_logic_vector(2 downto 0);			--give the binary count value from the vehicle counter 
C2 : out std_logic_vector(2 downto 0);      
C3 : out std_logic_vector(2 downto 0);
C4 : out std_logic_vector(2 downto 0);
in1 : out std_logic_vector(2 downto 0);			---give binary index value 
in2 : out std_logic_vector(2 downto 0);
in3 : out std_logic_vector(2 downto 0);
in4 : out std_logic_vector(2 downto 0));
end component;
type STATE_TYPE is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9);
signal Q,QPLUS : STATE_TYPE;
signal cnt8,cnt9,cnt0,cnt1,cnt2,cnt3,cnt4,cnt5,cnt6,cnt7: integer range 0 to 12 :=0;
type AR is array (0 to 3) of integer range 0 to 7; 
type AR1 is array (0 to 3) of std_logic_vector(2 downto 0);
type AR2 is array (0 to 3) of std_logic_vector(1 downto 0);
signal T : AR1 ; 
signal C1 : std_logic_vector(2 downto 0);
signal C2 : std_logic_vector(2 downto 0);
signal C3 : std_logic_vector(2 downto 0);
signal C4 : std_logic_vector(2 downto 0);
signal P :AR2 ;
signal id : AR1;
signal K ,i: AR ;
begin 
A : compare_block port map (CLK,RSTN,I1,I2,I3,I4,C1,C2,C3,C4,id(0),id(1),id(2),id(3));
K(0) <= to_integer(unsigned(C1)); --k(0) stores c1 maximum count 
K(1) <= to_integer(unsigned(C2));
K(2) <= to_integer(unsigned(C3));
K(3) <= to_integer(unsigned(C4));
i(0) <= to_integer(unsigned(id(0))); --k(0) stores c1 maximum count 
i(1) <= to_integer(unsigned(id(1)));
i(2) <= to_integer(unsigned(id(2)));
i(3) <= to_integer(unsigned(id(3)));
process (Q)
begin 
case Q is
when S0 =>
T(i(0)) <= "001"; --RYG order on state of the 
T(i(1)) <= "100";
T(i(2)) <= "100";
T(i(3)) <= "100";
P <= ("10","10","10","10");--order red,green
QPLUS <= S1;

when S1 =>   --blinking greeen
T(i(0)) <= "001"; --RYG order on state of the 
T(i(1)) <= "010";
T(i(2)) <= "100";
T(i(3)) <= "100";
P <= ("10","10","10","10");--order red,green
QPLUS <= S2;

when S2 => 
T(i(0)) <= "100"; --RYG order on state of the 
T(i(1)) <= "001";
T(i(2)) <= "100";
T(i(3)) <= "100";
P <= ("10","10","10","10");--order red,green
QPLUS <= S3;

when S3 => --blinking green
T(i(0)) <= "100"; --RYG order on state of the 
T(i(1)) <= "001";
T(i(2)) <= "010";
T(i(3)) <= "100";
P <= ("10","10","10","10");--order red,green
QPLUS <= S4;

when S4 => 
T(i(0)) <= "100"; --RYG order on state of the 
T(i(1)) <= "100";
T(i(2)) <= "001";
T(i(3)) <= "100";
P <= ("10","10","10","10");--order red,green
QPLUS <= S5;

when S5 => --blinking green
T(i(0)) <= "100"; --RYG order on state of the 
T(i(1)) <= "100";
T(i(2)) <= "001";
T(i(3)) <= "010";
P <= ("10","10","10","10");--order red,green
QPLUS <= S6;

when S6 => 
T(i(0)) <= "100"; --RYG order on state of the 
T(i(1)) <= "100";
T(i(2)) <= "100";
T(i(3)) <= "001";
P <= ("10","10","10","10");--order red,green
QPLUS <= S7;

when S7 => --blinking green
T(i(0)) <= "100"; --RYG order on state of the 
T(i(1)) <= "100";
T(i(2)) <= "100";
T(i(3)) <= "001";
P <= ("10","10","10","10");--order red,green
QPLUS <= S8;

when S8 =>
T(i(0)) <= "100"; --RYG order on state of the 
T(i(1)) <= "100";
T(i(2)) <= "100";
T(i(3)) <= "100";
P <= ("01","01","01","01");--order red,green
QPLUS <= S9;

when S9 =>
T(i(0)) <= "010"; --RYG order on state of the 
T(i(1)) <= "100";
T(i(2)) <= "100";
T(i(3)) <= "100";
P <= ("10","10","10","10");--order red,green
QPLUS <= S0;

end case;
end process;

process(CLK,RSTN)
begin

if(RSTN = '0') then 
Q <= S8;
elsif(CLK'event and CLK ='1') then
if(Q= S8 and cnt8 < 10) then
cnt8 <= cnt8+1;
elsif(Q= S8 and cnt8 = 10) then
cnt8 <= 0;
Q<=QPLUS;
end if;
if(Q= S9 and cnt9 < 5) then
cnt9 <= cnt9+1;
elsif(Q= S9 and cnt9 = 5) then
cnt9 <= 0;
Q<=QPLUS;
end if;
if(Q= S0 and cnt0 < 4*K(0)) then
cnt0 <= cnt0+1;
elsif(Q= S0 and cnt0 = 4*K(0)) then
cnt0 <= 0;
Q<=QPLUS;
end if;
if(Q= S1 and cnt1 < 5) then
cnt1 <= cnt1+1;
elsif(Q= S1 and cnt1 = 5) then
cnt1 <= 0;
Q<=QPLUS;
end if;

if(Q= S2 and cnt2 < 4*K(1)) then
cnt2 <= cnt2+1;
elsif(Q= S2 and cnt2 = 4*K(1)) then
cnt2 <= 0;
Q<=QPLUS;
end if;
if(Q= S3 and cnt3 < 5) then
cnt3 <= cnt3+1;
elsif(Q= S3 and cnt3 = 5) then
cnt3 <= 0;
Q<=QPLUS;
end if;
if(Q= S4 and cnt4 < 4*K(2)) then
cnt4 <= cnt4+1;
elsif(Q= S4 and cnt4 = 4*K(2)) then
cnt4 <= 0;
Q<=QPLUS;
end if;
 if(Q= S5 and cnt5 < 5) then
cnt5 <= cnt5+1;
elsif(Q= S5 and cnt5 = 5) then
cnt5 <= 0;
Q<=QPLUS;
end if;
if(Q= S6 and cnt6 < 4*K(3)) then
cnt6 <= cnt6+1;
elsif(Q= S6 and cnt6 = 4*K(3)) then
cnt6 <= 0;
Q<=QPLUS;
end if;
 if(Q= S7 and cnt7 < 5) then
cnt7 <= cnt7+1;
elsif(Q= S7 and cnt7 = 5) then
cnt7 <= 0;
Q<=QPLUS;
end if;
end if;
end process;
end functionality;