library ieee;
use ieee.std_logic_1164.all;
entity vehicle_counter2 is 
port(CLK :in std_logic;
RSTN : in std_logic;
I1 :in std_logic ;
	outp : out std_logic_vector(2 downto 0));
end entity vehicle_counter2 ;

architecture functionality of  vehicle_counter2 is 
type STATE_TYPE is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9);
signal Q,QPLUS : STATE_TYPE;
begin 
process (Q,I1)
begin 
case Q is
	when S0 => 
	outp <= "000";
	if (I1 = '1') then
	 QPLUS <= S1;
	 else QPLUS <= S0;
	 end if;
	when S1 =>									--here the high state
	outp <= "001";
	if (I1 = '0') then 
	QPLUS <= S2;
	else QPLUS <= S1;
	end if;
	when S2 => 									--low state
	outp <= "001";
	if (I1 = '1') then 
	QPLUS <= S3;
	else QPLUS <= S2;
	end if ;
	when S3 => 									--low state
	outp <= "010";
	if (I1 = '0') then 
	QPLUS <= S4;
	else QPLUS <= S3;
	end if ;
	when S4 => 									--low state
	outp <= "010";
	if (I1 = '1') then 
	QPLUS <= S5;
	else QPLUS <= S4;
	end if ;
	when S5 => 									--low state
	outp <= "011";
	if (I1 = '0') then 
	QPLUS <= S6;
	else QPLUS <= S5;
	end if ;
	when S6 => 									--low state
	outp <= "011";
	if (I1 = '1') then 
	QPLUS <= S7;
	else QPLUS <= S6;
	end if ;
	when S7 => 									--low state
	outp <= "100";
	if (I1 = '0') then 
	QPLUS <= S8;
	else QPLUS <= S7;
	end if ;
	when S8 => 									--low state
	outp <= "100";
	if (I1 = '1') then 
	QPLUS <= S9;
	else QPLUS <= S8;
	end if ;
	when S9 => 									--low state
	outp <= "101";
	if (I1 = '0') then 
	QPLUS <= S0;
	else QPLUS <= S9;
	end if ;
	when others =>
	QPLUS <= S0;
	end case ;
	end process ;
process(CLK,RSTN) 
begin 
if (RSTN = '0') then 
Q <= S0;
elsif (CLK'event and CLK = '1') then
Q<= QPLUS;
end if;
	end process;
	end functionality;